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    476 jobs - Page 1 of 15 (0.13 seconds)
    Inphi Corporation
    |
    Santa Clara, California
    - 2d ago
    RTL gate level simulations to coverage and signoffs.SystemVerilog (VMM, OVM or UVM).UVM preferred.Scripting perl python for flow support.Experience in uController based designs.Quick Learner...
    CompHealth
    |
    Randolph, Vermont
    - 1d ago
    You're close to two college towns with all the amenities college towns offer. Burlington, VT, home of UVM and Champlain College, and Hanover NH, home of Dartmouth College. You'll enjoy...
    University of Vermont
    |
    Burlington, Vermont
    - 2d ago
    To apply, please visit. www.uvmjobs.com. The University of Vermont is an Equal Opportunity Affirmative Action Employer.Applications, from women, veterans, individuals with disabilities and...
    Senior Mechanic | Burlington, VT, United States
    Senior Risk Analyst | Burlington, VT, United States
    Aricent
    |
    United States
    - 1d ago
    Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment. Enhance test benches and tests to achieve coverage goals. Apply formal...
    Northrop Grumman
    |
    Baltimore, Maryland
    - 2d ago
    Development of verification environments including the use of UVM, verification IP and System Verilog... development of verification environments including the use of UVM, verification IP and System Verilog...
    Mercuri Urval GmbH
    |
    De Pere, Wisconsin
    - 1d ago
    Projektmanager, Projektleiter Projektleiter (m w) OEM Automotive Von der Hauptniederlassung in Oberösterreich aus arbeiten Sie für einen Weltmarktführer im Tier 1 Automotive Bewerb...
    MaxLinear Inc.
    |
    Irvine, California
    - 1d ago
    Timing analysis in Cadence Synopsys design environments Directed and constrained random verification, UVM methodology Embedded systems FPGA emulation, lab debug and chip validation Project...
    ViaSat Inc
    |
    Marlborough, Massachusetts
    - 6d ago
    . years' experience with design and development of test structures using. System Verilog. 1. years' experience with. Universal Verification Methodology (UVM). Demonstrated ability to verify...
    SUNY Plattsburgh
    |
    Plattsburgh, New York
    - 5d ago
    Examples of Duties & Responsibilities. 1. Provide diagnostic and therapeutic speech language services for patients with neurological disorders (e.g., not limited to dementia, TBI, ...
    Quantenna, Inc
    |
    Fremont, California
    - 5d ago
    Create scripts to automate emulation runs. Qualifications. MSEE or BS with 2. year experience in Simulation Emulation (4. for SMTS). Good knowledge of system Verilog UVM. Reasonable expertise...
    Linear Technology
    |
    Colorado Springs, Colorado
    - 3d ago
    Validation of software and hardware products. Experience developing test plans and test benches, utilizing directed and constrained random techniques, preferably in a UVM environment. Advanced...
    Apple Inc
    |
    San Jose, California
    - 15d ago
    Create verification plans from specifications, review and refine to achieve coverage targets. Architect testbenches with maximum reusability in mind, and create UVM libraries. Debug failures...
    Boeing
    |
    El Segundo, California
    - 5h ago
    Experience with design architecture and detailed specification generation. Preferred Skills. Knowledge and competency of UVM. Thrive in working within a fast paced environment and work well in a...