476 jobs - Page 1 of 15 (0.13 seconds)
- 6d ago
. years' experience with design and development of test structures using. System Verilog. 1. years' experience with. Universal Verification Methodology (UVM). Demonstrated ability to verify...
Plattsburgh, New York
- 5d ago
Examples of Duties & Responsibilities. 1. Provide diagnostic and therapeutic speech language services for patients with neurological disorders (e.g., not limited to dementia, TBI, ...
- 5d ago
Create scripts to automate emulation runs. Qualifications. MSEE or BS with 2. year experience in Simulation Emulation (4. for SMTS). Good knowledge of system Verilog UVM. Reasonable expertise...
Colorado Springs, Colorado
- 3d ago
Validation of software and hardware products. Experience developing test plans and test benches, utilizing directed and constrained random techniques, preferably in a UVM environment. Advanced...
San Jose, California
- 15d ago
Create verification plans from specifications, review and refine to achieve coverage targets. Architect testbenches with maximum reusability in mind, and create UVM libraries. Debug failures...
El Segundo, California
- 5h ago
Experience with design architecture and detailed specification generation. Preferred Skills. Knowledge and competency of UVM. Thrive in working within a fast paced environment and work well in a...